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THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 1/22 thine electronics,inc. THC63LVD1027 85mhz 10bits dual lvds repeater general description the THC63LVD1027 lvds(low voltage differential signaling) repeater is designed to support pixel data transmission between host and flat panel display up to wuxga resolution. THC63LVD1027 receives the dual channel lvds data streams and transmits the lvds data through various line rate conversion modes, dual link input / dual link output, single link input / dual link output, and dual link input / single link output. at a transmit clock frequency of 85mhz, 30bits of rgb data and 5bits of timing and control data (hsync, vsync, de) are transmitted at an effective rate of 595mbps per lvds channel. features ? up to 85mhz 10bit dual channel lvds receiver ? up to 85mhz 10bit dual channel lvds transmitter ? wide lvds input skew margin: 480ps at 75mhz ? accurate lvds output timing: 250ps at 75mhz ? reduced swing lvds output mode supported to suppress the system emi ? various line rate conversion modes supported dual link input / dual link output [clkout=1x clkin] single link input / dual link output [clkout=1/2x clkin] dual link input / single link output [clkout=2x clkin] ? distribution (signal duplication) mode supported ? power down mode supported ? 3.3v single voltage power supply ? no external components required for plls ? 64pin tssop with exposed pad (0.5mm lead pitch) block diagram lvds-rx de-serialize pll lvds-rx de-serialize lvds-tx serialize lvds-tx serialize pll inter-link multiplex & de-multi- plex ldo regulator pll thine ? THC63LVD1027 lvds 1st link 10bit pixel clock 85mhz max lvds 2nd link clock 10bit pixel 85mhz max lvds 1st link 10bit pixel clock 85mhz max lvds 2nd link clock 10bit pixel 85mhz max 3.3v power supply decoupling capacitor dual in / dual out mode 85mhz 85mhz 85mhz 85mhz THC63LVD1027 distribution mode 85mhz 85mhz 85mhz THC63LVD1027 single in / dual out mode 42.5mhz 42.5mhz 85mhz THC63LVD1027 dual in / single out mode 42.5mhz 85mhz 42.5mhz THC63LVD1027
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 2/22 thine electronics,inc. pin out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 rs cap gnd vdd ra1+ ra1? rb1+ rb1? rc1+ rc1? rclk1+ rclk1? rd1+ rd1? re1+ re1? ra2+ ra2? rb2+ rb2? rc2+ rc2? rclk2+ rclk2? rd2+ rd2? re2+ re2? cap gnd vdd pd mode0 mode1 vdd gnd te2+ te2? td2+ td2? tclk2+ tclk2? tc2+ tc2? tb2+ tb2? ta2+ ta2? te1+ te1? td1+ td1? tclk1+ tclk1? tc1+ tc1? tb1+ tb1? ta1+ ta1? gnd vdd gnd cap tssop64 exposed pad top view 65 gnd (exposed pad)
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 3/22 thine electronics,inc. pin description pin name direction type description ra1+/? input lvds lvds data input for channel a of 1st link rb1+/? lvds data input for channel b of 1st link rc1+/? lvds data input for channel c of 1st link rd1+/? lvds data input for channel d of 1st link re1+/? lvds data input for channel e of 1st link rclk1+/? lvds clock input for 1st link ra2+/? lvds data input for channel a of 2nd link rb2+/? lvds data input for channel b of 2nd link rc2+/? lvds data input for channel c of 2nd link rd2+/? lvds data input for channel d of 2nd link re2+/? lvds data input for channel e of 2nd link rclk2+/? lvds clock input for 2nd link in distribution and single-in/dual-out mode, rclk2+/- must be hi-z. (see ? mode selection ? below in this page.) ta1+/? output lvds data output for channel a of 1st link tb1+/? lvds data output for channel b of 1st link tc1+/? lvds data output for channel c of 1st link td1+/? lvds data output for channel d of 1st link te1+/? lvds data output for channel e of 1st link tclk1+/? lvds clock output for 1st link ta2+/? lvds data output for channel a of 2nd link tb2+/? lvds data output for channel b of 2nd link tc2+/? lvds data output for channel c of 2nd link td2+/? lvds data output for channel d of 2nd link te2+/? lvds data output for channel e of 2nd link tclk2+/- lvds clock output for 2nd link pd input lv-ttl power down h: normal operation l: power down state, all lvds output signals turn to hi-z rs lvds output swing level selection h: normal swing l: reduced swing mode1 mode0 mode selection in distribution and single-in/dual-out mode, rclk2+/- must be hi-z. vdd power ? 3.3v power supply pins gnd ground pins (exposed pad is also ground) cap decoupling capacitor pins these pins should be connected to external decoupling capacitors ( c cap ). recommended c cap is 0.1uf mode1 mode0 rclk2+/- description l l clkin dual-in / dual-out mode l l hi-z distribution mode h l hi-z single-in / dual-out mode l h clkin dual-in / single-out mode h h - reserved
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 4/22 thine electronics,inc. mode setting input/output rclk2+/- mode1 (input mode) mode0 (output mode) h: single l: dual h: single l: dual dual-in/dual-out (fig.2-1, 3-1) clk in l l distribution (fig.2-2, 3-2) hi-z l l single-in/dual-out (fig.2-3, 3-3) hi-z h l dual-in/single-out (fig.2-4, 3-4) clk in l h reserved -- h h fig2-1 fig2-2 fig2-3 fig2-4 dual-in / dual-out ta1+/- tb1+/- tc1+/- td1+/- te1+/- tclk1+/- ta2+/- tb2+/- tc2+/- td2+/- te2+/- tclk2+/- =tclk1+/- clk frequency f data rate f clk frequency f data rate f clk frequency f data rate f ra1+/- rb1+/- rc1+/- rd1+/- re1+/- rclk1+/- ra2+/- rb2+/- rc2+/- rd2+/- re2+/- rclk2+/- clk frequency f data rate f distribution mode ta1+/- tb1+/- tc1+/- td1+/- te1+/- tclk1+/- ta2+/- tb2+/- tc2+/- td2+/- te2+/- tclk2+/- same data clk frequency f data rate f clk frequency f data rate f =tclk1+/- clk frequency f data rate f ra1+/- rb1+/- rc1+/- rd1+/- re1+/- rclk1+/- ra2+/- rb2+/- rc2+/- rd2+/- re2+/- rclk2+/- must be hi-z hi-z single-in / dual-out ta1+/- tb1+/- tc1+/- td1+/- te1+/- tclk1+/- ta2+/- tb2+/- tc2+/- td2+/- te2+/- tclk2+/- clk frequency f/2 data rate f/2 clk frequency f data rate f ra1+/- rb1+/- rc1+/- rd1+/- re1+/- rclk1+/- ra2+/- rb2+/- rc2+/- rd2+/- re2+/- rclk2+/- must be hi-z clk frequency f/2 data rate f/2 hi-z signal flow for each setting dual-in / single-out ta1+/- tb1+/- tc1+/- td1+/- te1+/- tclk1+/- ta2+/- tb2+/- tc2+/- td2+/- te2+/- tclk2+/- clk frequency 2f data rate 2f clk frequency f data rate f ra1+/- rb1+/- rc1+/- rd1+/- re1+/- rclk1+/- ra2+/- rb2+/- rc2+/- rd2+/- re2+/- rclk2+/- clk frequency f data rate f hi-z
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 5/22 thine electronics,inc. output control / fail safe THC63LVD1027 has a function to control output depending on lvds input condition. *: don?t care #: if a particular input data pair is hi-z, the corresponding output data become l according to lvds dc spec. for fail-safe purpose, all lvds input pins are connected to vdd via resistance for detecting state of hi-z. pd rclk1+/- rclk2+/- output l * * all hi-z h hi-z * all hi-z h clk in clk in refer to p.4 mode setting # h clk in hi-z refer to p.4 mode setting # vdd lvds input buffer internal circuit of THC63LVD1027
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 6/22 thine electronics,inc. absolute maximum ratings operating conditions parameter min max unit power supply voltage ?0.3 4.0 v lvds input voltage -0.3 v dd +0.3 v junction temperature ? 125 oc storage temperature ?55 125 oc reflow peak temperature / time ? 260 / 10sec. oc maximum power dissipation @+25 ? 2.5 w symbol parameter min typ max unit t a ambient temperature ?20 25 70 oc v dd power supply voltage 3.0 3.3 3.6 v f clk dual-in / dual-out input 20 ? 85 mhz output 20 ? 85 mhz distribution input 20 ? 85 mhz output 20 ? 85 mhz single-in / dual-out input 40 ? 85 mhz output 20 ? 42.5 mhz dual-in / single-out input 20 ? 42.5 mhz output 40 ? 85 mhz ? c
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 7/22 thine electronics,inc. power dissipation symbol parameter conditions min typ max unit i ccw operating current (worst case pattern) fig1 dual-in/dual-out clkin =40 mhz r l_tx = 100 ? cl=5pf rs=v dd fig2 ? ? 265 ma clkin =65 mhz ? ? 305 ma clkin =75 mhz ? ? 325 ma clkin =85 mhz ? ? 340 ma distribution clkin =40 mhz ? ? 215 ma clkin =65 mhz ? ? 235 ma clkin =75 mhz ? ? 245 ma clkin =85 mhz ? ? 260 ma single-in/dual-out clkin =40 mhz ? ? 175 ma clkin =65 mhz ? ? 190 ma clkin =75 mhz ? ? 200 ma clkin =85 mhz ? ? 210 ma dual-in/single-out clkin =20 mhz ? ? 215 ma clkin =32.5 mhz ? ? 235 ma clkin =37.5 mhz ? ? 245 ma clkin =42.5 mhz ? ? 260 ma i ccs power down current ? ? ? ? 8 ma fig1. test pattern (lvds output full toggle pattern) txy+ x= a, b, c, d, e y=1,2 tclky+ 5pf 100 ? txy+ txy - lvds output load fig2. lvds output load y=1,2 x= a, b, c, clk, d, e
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 8/22 thine electronics,inc. electrical characteristics THC63LVD1027 dc specifications lvds receiver dc specifications lvds transmitter dc specifications symbol parameter conditions min. typ. max. units vcap capacitor pin appearance voltage c cap = 0.1f ? 1.8 ? v v il_ttl lv-ttl input low voltage ? gnd ? 0.8 v ih_ttl lv-ttl input high voltage ? 2.0 ? vdd i in_ttl lv-ttl input leakage current ? -4 ? +4 ? a symbol parameter conditions min. typ. max. units v in_rx lvds-rx input voltage range ? 0.3 ? 2.1 v v ic_rx lvds-rx common voltage ? 0.6 1.2 1.8 v th_rx lvds-rx differential high threshold v ic_rx = 1.2v ? ? +100 mv v tl_rx lvds-rx differential low threshold -100 ? ? | v id_rx | lvds-rx differential input voltage ? 100 ? 600 i in_rx lvds-rx input leakage current ? -0.3 ? 0.3 ma symbol parameter conditions min. typ. max. units v oc_tx lvds-tx common voltage r l_tx = 100 ? ? 1.125 1.25 1.375 v ? v oc_tx change in voc between complementary output states ? ? ? 35 mv | v od_tx | lvds-tx differential output voltage normal swing 250 350 450 mv reduced swing 100 200 300 ? v od_tx change in vod between complementary output states ? ? ? 35 mv i os_tx lvds-tx output short current vout= gnd -24 ? ? ma i oz_tx lvds-tx output tri-state current pd= gnd vout= gnd to vcc -10 ? +10 ua
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 9/22 thine electronics,inc. THC63LVD1027 ac characteristics symbol parameter conditions min typ max unit t lt phase lock loop set time (fig.3) ? ? ? ? 10 ms t dl data latency (fig.4) dual-in/dual-out clkin=75mhz 9 t rcp + 3 9 t rcp + 5 9 t rcp + 7 ns distribution clkin=75mhz 9 t rcp + 3 9 t rcp + 5 9 t rcp + 7 single-in/dual-out clkin=75mhz (11+2/7) t rcp + 3 (11+2/7) t rcp + 5 (11+2/7) t rcp + 7 dual-in/single-out clkin=37.5mhz (8+5/14) t rcp + 3 (8+5/14) t rcp + 5 (8+5/14) t rcp + 7 t deh de input high time (fig.5) single-in/ dual-out ? 2 t rcp ? ? ns t del de input low time (fig.5) ? 2 t rcp ? ? t deint de input period (fig.5) ? 4 t rcp must be 2n t rcp (n=integer) ? ac timing diagrams 2.0v t lt rclk1+/- pd tclkx+/- fig.3. phase lock loop set time vdd 3.0v note: 1) vdifftc = (tclk+) - (tclk-) v difftc = 0v x=1,2
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 10/22 thine electronics,inc. ac timing diagrams (continued) v diffrc = 0v t dl rclk1+ note: 1) vdiffrc = (rclk+) - (rclk-) fig.4. data latency current data ryx+/- x=1,2 y= a, b, c, d, e tclk1+ v difftc = 0v 2) vdifftc = (tclk+) - (tclk-) current data tyx+/- x=1,2 y= a, b, c, d, e rc1+ rclk1+ fig.5. single link input / dual link output mode rc1(de) input timing de t deint t deh t del de de de de de
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 11/22 thine electronics,inc. lvds receiver ac characteristics lvds receiver input timing symbol parameter conditions min typ max unit t rcp lvds clock period ? 11.76 ? 50 ns t rch lvds clock high duration ? 2/7 t rcp 4/7 t rcp 5/7 t rcp t rcl lvds clock low duration ? 2/7 t rcp 3/7 t rcp 5/7 t rcp t rsup lvds data input setup margin clkin =75 mhz 480 ? ? ps t rhld lvds data input hold margin clkin =75 mhz 480 ? ? t rip6 lvds data input position 6 ? 2/7 t rcp - t rhld 2/7 t rcp 2/7 t rcp + t rsup ps t rip5 lvds data input position 5 ? 3/7 t rcp - t rhld 3/7 t rcp 3/7 t rcp + t rsup t rip4 lvds data input position 4 ? 4/7 t rcp - t rhld 4/7 t rcp 4/7 t rcp + t rsup t rip3 lvds data input position 3 ? 5/7 t rcp - t rhld 5/7 t rcp 5/7 t rcp + t rsup t rip2 lvds data input position 2 ? 6/7 t rcp - t rhld 6/7 t rcp 6/7 t rcp + t rsup t rip1 lvds data input position 1 ? 7/7 t rcp - t rhld 7/7 t rcp 7/7 t rcp + t rsup t rip0 lvds data input position 0 ? 8/7 t rcp - t rhld 8/7 t rcp 8/7 t rcp + t rsup t ck12 skew time between rclk1 and rclk2 (fig.6) ? -0.3 t rcp ? 0.3 t rcp ps t rip3 ryx+/- rclkx+ t rip4 t rip5 t rip6 t rip2 t rip0 t rip1 t rcp d<5>d<6> d<4> d<3> d<2> d?<1> d?<0> t rch t rcl rclkx- x=1,2 y= a, b, c, d, e ry1+/- skew margin is the one between rclk1+/- and ry1+/-. ry2+/- skew margin is the one between rclk2+/- and ry2+/-.
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 12/22 thine electronics,inc. lvds receiver input timing (continued) v diffrc = 0v t ck12 (rclk1+)-(rclk1-) v diffrc = 0v (rclk2+)-(rclk2-) fig.6. skew time between rclk1 and rclk2 note: 1) vdiffrc = (rclk+) - (rclk-)
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 13/22 thine electronics,inc. lvds transmitter ac characteristics lvds transmitter output timing symbol parameter conditions min typ max unit t tcp lvds clock period ? 11.76 ? 50 ns t tch lvds clock high duration ? ? 4/7 t tcp ? t tcl lvds clock low duration ? ? 3/7 t tcp ? t tsup lvds data output setup clkout =75 mhz ? ? 250 ps t thld lvds data output hold clkout =75 mhz ? ? 250 t top6 lvds data output position 6 ? 2/7 t tcp - t thld 2/7 t tcp 2/7 t tcp + t tsup ps t top5 lvds data output position 5 ? 3/7 t tcp - t thld 3/7 t tcp 3/7 t tcp + t tsup t top4 lvds data output position 4 ? 4/7 t tcp - t thld 4/7 t tcp 4/7 t tcp + t tsup t top3 lvds data output position 3 ? 5/7 t tcp - t thld 5/7 t tcp 5/7 t tcp + t tsup t top2 lvds data output position 2 ? 6/7 t tcp - t thld 6/7 t tcp 6/7 t tcp + t tsup t top1 lvds data output position 1 ? 7/7 t tcp - t thld 7/7 t tcp 7/7 t tcp + t tsup t top0 lvds data output position 0 ? 8/7 t tcp - t thld 8/7 t tcp 8/7 t tcp + t tsup t lvt lvds transition time (fig7) ? ? 0.6 1.5 ns tyx+/- tclkx+ tclkx- x=1,2 y= a, b, c, d, e ty1+/- output timing is the one between tclk1+/- and ty1+/-. ty2+/- output timing is the one between tclk2+/- and ty2+/-. 20% 80% 20% 80% t lvt v difft t lvt note: 1) vdifft = (tyx+) - (tyx-) fig7. lvds transition time t top3 t top4 t top5 t top6 t top2 t top0 t top1 t tcp d<5>d<6> d<4> d<3> d<2> d?<1> d?<0> t tch t tcl y=1,2 x= a, b, c, clk, d, e
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 14/22 thine electronics,inc. lvds data mapping dual-in / dual-out mode g2 [4] r2 [9] r2 [8] r2 [7] r2 [5] r2 [4]r2 [6] de vsync hsync b2 [9] b2 [7] b2 [6]b2 [8] b2 [5] b2 [4] g2 [9] g2 [8] r2 [5]g2 [7] data21 b2 [3] b2 [2] g2 [3] r2 [3] r2 [2]g2 [2] data22 b2 [1] b2 [0] g2 [1] r2 [1] r2 [0]g2 [0] rc2+/? rb2+/? rd2+/? re2+/? ra2+/? r1 [9]g1 [4] r1 [7]r1 [8] r1 [5]r1 [6] g3 [4]r1 [4] r3 [9] r3 [8] r3 [7] r3 [5] r3 [4]r3 [6] vsyncde b1 [9]hsync b1 [7]b1 [8] deb1 [6] vsync hsync b3 [9] b3 [7] b3 [6]b3 [8] b1 [4]b1 [5] g1 [8]g1 [9] g1 [6]g1 [7] b3 [5]g1 [5] b3 [4] g3 [9] g3 [8] g3 [6] g3 [5]g3 [7] b1 [3]data11 g1 [3]b1 [2] r1 [3]g1 [2] data11r1 [2] b3 [3] b3 [2] g3 [3] r3 [3] r3 [2]g3 [2] b1 [1]data12 g1 [1]b1 [0] r1 [1]g1 [0] data12r1 [0] b3 [1] b3 [0] g3 [1] r3 [1] r3 [0]g2 [0] rc1+/? rb1+/? rd1+/? re1+/? ra1+/? g2 [6] g4 [4] r4 [9] r4 [8] r4 [7] r4 [5] r4 [4]r4 [6] de vsync hsync b4 [9] b4 [7] b4 [6]b4 [8] b4 [5] b4 [4] g4 [9] g4 [8] g4 [5]g4 [7] data21 b4 [3] b4 [2] g4 [3] r4 [3] r4 [2]g4 [2] data22 b4 [1] b4 [0] g4 [1] r4 [1] r4 [0]g4 [0] g4 [6] g2 [4] r2 [9] r2 [8] r2 [7] r2 [5] r2 [4]r2 [6] de vsync hsync b2 [9] b2 [7] b2 [6]b2 [8] b2 [5] b2 [4] g2 [9] g2 [8] g2 [5]g2 [7] data21 b2 [3] b2 [2] g2 [3] r2 [3] r2 [2]g2 [2] data22 b2 [1] b2 [0] g2 [1] r2 [1] r2 [0]g2 [0] tc2+/? tb2+/? td2+/? te2+/? ta2+/? r1 [9]g1 [4] r1 [7]r1 [8] r1 [5]r1 [6] g3 [4]r1 [4] r3 [9] r3 [8] r3 [7] r3 [5] r3 [4]r3 [6] vsyncde b1 [9]hsync b1 [7]b1 [8] deb1 [6] vsync hsync b3 [9] b3 [7] b3 [6]b3 [8] b1 [4]b1 [5] g1 [8]g1 [9] g1 [6]g1 [7] b3 [5]g1 [5] b3 [4] g3 [9] g3 [8] g3 [6] g3 [5]g3 [7] b1 [3]data11 g1 [3]b1 [2] r1 [3]g1 [2] data11r1 [2] b3 [3] b3 [2] g3 [3] r3 [3] r3 [2]g3 [2] b1 [1]data12 g1 [1]b1 [0] r1 [1]g1 [0] data12r1 [0] b3 [1] b3 [0] g3 [1] r3 [1] r3 [0]g2 [0] tc1+/? tb1+/? td1+/? te1+/? ta1+/? g2 [6] g4 [4] r4 [9] r4 [8] r4 [7] r4 [5] r4 [4]r4 [6] de vsync hsync b4 [9] b4 [7] b4 [6]b4 [8] b4 [5] b4 [4] g4 [9] g4 [8] g4 [5]g4 [7] data21 b4 [3] b4 [2] g4 [3] r4 [3] r4 [2]g4 [2] data22 b4 [1] b4 [0] g4 [1] r4 [1] r4 [0]g4 [0] g4 [6] lvds-rx input mapping lvds-tx output mapping ( regardless of the data latency ) rclk1+/? rclk2+/? tclk1+/? tclk2+/? data bits ?data11, data12, data21, data22? are available for additional data transmission.
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 15/22 thine electronics,inc. distribution mode in distribution mode, rclk2+/- must be high-z. no care no care no care no care no care r1 [9]g1 [4] r1 [7]r1 [8] r1 [5]r1 [6] g2 [4]r1 [4] r2 [9] r2 [8] r2 [7] r2 [5] r2 [4]r2 [6] vsyncde b1 [9]hsync b1 [7]b1 [8] deb1 [6] vsync hsync b2 [9] b2 [7] b2 [6]b2 [8] b1 [4]b1 [5] g1 [8]g1 [9] g1 [6]g1 [7] b2 [5]g1 [5] b2 [4] g2 [9] g2 [8] g2 [6] g2 [5]g2 [7] b1 [3]data11 g1 [3]b1 [2] r1 [3]g1 [2] data11r1 [2] b2 [3] b2 [2] g2 [3] r2 [3] r2 [2]g2 [2] b1 [1]data12 g1 [1]b1 [0] r1 [1]g1 [0] data12r1 [0] b2 [1] b2 [0] g2 [1] r2 [1] r2 [0]g2 [0] rc1+/? rb1+/? rd1+/? re1+/? ra1+/? r1 [9]g1 [4] r1 [7]r1 [8] r1 [5]r1 [6] g2 [4]r1 [4] r2 [9] r2 [8] r2 [7] r2 [5] r2 [4]r2 [6] vsyncde b1 [9]hsync b1 [7]b1 [8] deb1 [6] vsync hsync b2 [9] b2 [7] b2 [6]b2 [8] b1 [4]b1 [5] g1 [8]g1 [9] g1 [6]g1 [7] b2 [5]g1 [5] b2 [4] g2 [9] g2 [8] g2 [6] g2 [5]g2 [7] b1 [3]data11 g1 [3]b1 [2] r1 [3]g1 [2] data11r1 [2] b2 [3] b2 [2] g2 [3] r2 [3] r2 [2]g2 [2] b1 [1]data12 g1 [1]b1 [0] r1 [1]g1 [0] data12r1 [0] b2 [1] b2 [0] g2 [1] r2 [1] r2 [0]g2 [0] tc1+/? tb1+/? td1+/? te1+/? ta1+/? lvds-rx input mapping lvds-tx output mapping (regardless of the data latency) tclk1+/? tclk2+/? r1 [9]g1 [4] r1 [7]r1 [8] r1 [5]r1 [6] g2 [4]r1 [4] r2 [9] r2 [8] r2 [7] r2 [5] r2 [4]r2 [6] vsyncde b1 [9]hsync b1 [7]b1 [8] deb1 [6] vsync hsync b2 [9] b2 [7] b2 [6]b2 [8] b1 [4]b1 [5] g1 [8]g1 [9] g1 [6]g1 [7] b2 [5]g1 [5] b2 [4] g2 [9] g2 [8] g2 [6] g2 [5]g2 [7] b1 [3]data11 g1 [3]b1 [2] r1 [3]g1 [2] data11r1 [2] b2 [3] b2 [2] g2 [3] r2 [3] r2 [2]g2 [2] tc2+/? tb2+/? td2+/? ta2+/? b1 [1]data12 g1 [1]b1 [0] r1 [1]g1 [0] data12r1 [0] b2 [1] b2 [0] g2 [1] r2 [1] r2 [0]g2 [0] te2+/? rc2+/? rclk2+/? rb2+/? rd2+/? re2+/? ra2+/? rclk1+/? hi-z data bits ?data11, data12? are available for additional data transmission.
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 16/22 thine electronics,inc. single-in / dual-out mode in single-in / dual-out mode, rclk2+/- must be high-z. rc2+/? rclk2+/? rb2+/? rd2+/? re2+/? ra2+/? lvds-rx input mapping lvds-tx output mapping ( regardless of the data latency ) hi-z no care no care no care no care no care r1 [9]g1 [4] r1 [7]r1 [8] r1 [5]r1 [6] g2 [4] r1 [4] r2 [9] r2 [8] r2 [7] r2 [5] r2 [4]r2 [6] vsyncde b1 [9]hsync b1 [7]b1 [8] de b1 [6] vsync hsync b2 [9] b2 [7] b2 [6]b2 [8] b1 [4]b1 [5] g1 [8]g1 [9] g1 [6]g1 [7] b2 [5] g1 [5] b2 [4] g2 [9] g2 [8] g2 [6] g2 [5]g2 [7] b1 [3]data11 g1 [3]b1 [2] r1 [3]g1 [2] data11 r1 [2] b2 [3] b2 [2] g2 [3] r2 [3] r2 [2]g2 [2] b1 [1]data12 g1 [1]b1 [0] r1 [1]g1 [0] data12 r1 [0] b2 [1] b2 [0] g2 [1] r2 [1] r2 [0]g2 [0] rc1+/? rb1+/? rd1+/? re1+/? ra1+/? ta1+/? tclk1+/? g1 [4] r1 [9] r1 [8] r1 [7] r1 [6] r1 [5] r1 [4] tc1+/? de vsync hsync b1 [9] b1 [8] b1 [7] b1 [6] tb1+/? b1 [5] b1 [4] g1 [9] g1 [8] g1 [7] g1 [6] g1 [5] td1+/? data11 b1 [3] b1 [2] g1 [3] g1 [2] r1 [3] r1 [2] te1+/? data12 b1 [1] b1 [0] g1 [1] g1 [0] r1 [1] r1 [0] ta2+/? g2 [4] r2 [9] r2 [8] r2 [7] r2 [6] r2 [5] r2 [4] tc2+/? de vsync hsync b2 [9] b2 [8] b2 [7] b2 [6] tb2+/? b2 [5] b2 [4] g2 [9] g2 [8] g2 [7] g2 [6] g2 [5] td2+/? data11 b2 [3] b2 [2] g2 [3] g2 [2] r2 [3] r2 [2] te2+/? data12 b2 [1] b2 [0] g2 [1] g2 [0] r2 [1] r2 [0] rclk1+/? tclk2+/? data bits ?data11, data12? are available for additional data transmission.
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 17/22 thine electronics,inc. single link input ( regardless of the data latency ) rclk1+ b d a b c d ry1+/- a c dual link output tclk1+ ty1+/- ty2+/- rc1+/- tc2+/- tc1+/- de schematic diagram of de transition de de de de de de de de tclk2+ single-in / dual-out mode uses de signal l-to-h-edge to start distribution of input data. y= a, b, c, d, e
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 18/22 thine electronics,inc. dual-in / single-out mode lvds-rx input mapping lvds-tx output mapping ( regardless of the data latency ) ra1+/? g1 [4] r1 [9] r1 [8] r1 [7] r1 [6] r1 [5] r1 [4] rc1+/? de vsync hsync b1 [9] b1 [8] b1 [7] b1 [6] rb1+/? b1 [5] b1 [4] g1 [9] g1 [8] g1 [7] g1 [6] g1 [5] rd1+/? data11 b1 [3] b1 [2] g1 [3] g1 [2] r1 [3] r1 [2] re1+/? data12 b1 [1] b1 [0] g1 [1] g1 [0] r1 [1] r1 [0] ra2+/? g2 [4] r2 [9] r2 [8] r2 [7] r2 [6] r2 [5] r2 [4] rc2+/? de vsync hsync b2 [9] b2 [8] b2 [7] b2 [6] rb2+/? b2 [5] b2 [4] g2 [9] g2 [8] g2 [7] g2 [6] g2 [5] rd2+/? data21 b2 [3] b2 [2] g2 [3] g2 [2] r2 [3] r2 [2] re2+/? data22 b2 [1] b2 [0] g2 [1] g2 [0] r2 [1] r2 [0] r1 [9]g1 [4] r1 [7]r1 [8] r1 [5]r1 [6] g2 [4] r1 [4] r2 [9] r2 [8] r2 [7] r2 [5] r2 [4]r2 [6] vsyncde b1 [9]hsync b1 [7]b1 [8] de b1 [6] vsync hsync b2 [9] b2 [7] b2 [6]b2 [8] b1 [4]b1 [5] g1 [8]g1 [9] g1 [6]g1 [7] b2 [5] g1 [5] b2 [4] g2 [9] g2 [8] g2 [6] g2 [5]g2 [7] b1 [3]data11 g1 [3]b1 [2] r1 [3]g1 [2] data21 r1 [2] b2 [3] b2 [2] g2 [3] r2 [3] r2 [2]g2 [2] b1 [1]data12 g1 [1]b1 [0] r1 [1]g1 [0] data22 r1 [0] b2 [1] b2 [0] g2 [1] r2 [1] r2 [0]g2 [0] tc1+/? tb1+/? td1+/? te1+/? ta1+/? tc2+/? tclk2+/? tb2+/? td2+/? te2+/? ta2+/? hi-z hi-z hi-z hi-z hi-z hi-z rclk1+/? rclk2+/? tclk1+/? data bits ?data11, data12, data21, data22? are available for additional data transmission.
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 19/22 thine electronics,inc. note 1)lvds input pin connection when lvds line is not drived from the previous device, the line is pulled up to 3.3v internally in THC63LVD1027. this can cause violation of absolute maximum ratings to the previous lvds tx device whose operating condition is lower voltage power supply than 3.3v. this phenomenon may happen at power on phase of the whole system includ- ing THC63LVD1027. one solution for this problem is pd=l control during no lvds input period because pull-up resistors are cut off at power down state. 2)power on sequence don?t input rclk#+/- before THC63LVD1027 is on in order to keep absolute maximum ratings. vdd lvds input buffer internal circuit of THC63LVD1027 low vdd lvds tx THC63LVD1027 or lvds tx integrated device lvds tx side pcb lvds rx side pcb
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 20/22 thine electronics,inc. 3)cable connection and disconnection don?t connect and disconnect the lvds cable, when the power is supplied to the system. 4)gnd connection connect the each gnd of the pcb which transmitter, receiver and THC63LVD1027 on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 5)multi drop connection multi drop connection is not recommended. 6)asynchronous use asynchronous use such as following systems are not recommended. page.11 tck12 spec should be kept. asynchronous use such as following systems are not recommended. lvds rx THC63LVD1027 tclk1,2- tclk1,2+ lvds rx lvds tx THC63LVD1027 rclk1+/- rclk2+/- ic lvds tx clkout dataout clkout dataout lvds rx THC63LVD1027 tclk1+/- tclk2+/- ic lvds rx clkin datain datain
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 21/22 thine electronics,inc. package 0.20 typ 0.50 0.10 8.10 0.20 6.10 0.10 1.10 max 0.90 0.10 0.05 ~ 0.15 0.25 detail of lead end 1 s 0.10 s unit: mm bsc 1.00 ref 0.60 0.15 17.00 0.10 4.45 ref 3 . 0 5 r e f 0 ~ 8 deg exposed pad is gnd and must be soldered to pcb. thc63lv1027
THC63LVD1027_rev.2.0_e copyright?2010 thine electronics, inc. 22/22 thine electronics,inc. notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. this material contains our copy right, know-how or other proprietary. copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. this product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various types of safety equipment, please do it after applying appropriate measures to the product. 6. despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign exchange and foreign trade control law. thine electronics, inc. e-mail : sales@thine.co.jp

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